40G QSFP+ ER4 Optical Transceiver - Fiber Optic Cabling Management

40G QSFP+ ER4 Optical Transceiver

396 Fibers FTTH Splitter Cabinet with Insertion Module PLC Splitter - Type B -rear side
396 Fibers FTTH Splitter Cabinet with Insertion Module PLC Splitter – Type B
576 Fibers FTTH Splitter Cabinet PLC Splitter
576 Fibers FTTH Splitter Cabinet with 72pcs of 1×8 Insertion Module PLC Splitter


LINKWELL 40G QSFP+ ER4 40km optical transceiver is designed for 40G Ethernet and OTN OTU3 links reach up to 40km over Single-Mode Fiber (SMF). It is compliant with the QSFP+ MSA, IEEE 802.3bm 40GBASE-ER4, and OTU3 requirements. The LINKWELL technology enables the integration of 4 transmitters, 4 receivers and an optical MUX/DEMUX into a small form factor package..



  • 4 channels full-duplex transceiver modules
  • Transmission data rate up to 11Gbps per channel
  • Compliant with 40GBASE-ER4
  • 4 channels DFB-based CWDM cooling transmitter
  • 4 channels APD ROSA
  • Low power consumption < 3.5W
  • Hot-pluggable QSFP+ form-factor
  • Transmission distance up to 40KM
  • Duplex LC receptacles
  • Operating case temperature range 0°C to +70°C
  • 3.3V power supply voltage


  • 40GBASE-ER4
  • Infiniband QDR and DDR interconnects

Absolute Maximum Rating

These values represent the damage threshold of the module. Stress in excess of any of the individual Absolute Maximum Ratings can cause immediate catastrophic damage to the module even if all other parameters are within Recommended Operating Conditions.

Power Supply VoltageVCC-0.3+3.6V
Input VoltageVin-0.3Vcc+0.3
Storage TemperatureTc-20+85C
Operating Case TemperatureTc0+70C
Relative HumidityRh585%
Damage Threshold, each LaneTH5.5dBm

Recommended Operating Environment

Recommended Operating Environment specifies parameters for which the electrical and optical characteristics hold unless otherwise noted.

Power Supply VoltageVCC3.133.303.47V
Operating Case TemperatureTc070C
Data Rate per Lanefd9.9510.312511.15Gbps
Power DissipationPm3.53.8W

Optical Characteristics

Lane WavelengthL01264.512711277.5nm
Total Average Launch PowerPt10.5dBm
Average launch power, each lanePavg-2.74.5dBm
Optical Modulation Amplitude (OMA), each lane1OMA-1.35dBm
Difference in Launch PowerPtxd4.7dB
Launch Power in OMA-0.5dBm
Extinction RatioER4.5dB
TDP, each laneTdp2.6dB
Average launch power of OFF-30dB
Eye Mask coordinates2: X1, X2, X3, Y1, Y2, Y3{0.25,0.4,0.45,0.25,}
Damage Threshold, each lane3THd-6dBm
Average Receive Power, each lane-22.2-4.5dBm
Receive Power (OAM), each lane-4.0dBm
Receiver Sensitivity (OMA), each Lane (BER = 5×10-5)SEN1-19dBm
Stressed Receiver Sensitivity (OMA), each lane4 (BER = 5×10-12)SEN3-16.8dBm
Difference in Receive Power between any Two Lanes (OMA)Prx,diff3.8dB
LOS AssertLOSA-35dBm
LOS DeassertLOSD-19dB
LOS HysteresisLOSH0.5dB

Electrical Characteristics

Transmitter (each lane)
Single-ended Input Voltage Tolerance-0.34.0V
AC Common-Mode Input Voltage Tolerance15mW
Differential Input Voltage50mVpp
Differential Input Voltage SwingVin900mVpp
Differential Input ImpedanceZin90100110Ohm
Receiver (each lane)
Single-ended Output Voltage-0.34.0V
AC Common Mode Output Voltage7.5mV
Differential Output Voltage Swing300850mVpp
Differential Output Impedance90100110Ohm


Power-on Initialization Time is the time from when the power supply voltages reach and remain above the minimum recommended operating supply voltages to the time when the module is fully functional

Pin Description

PIN #SymbolDescription
2Tx2nTransmitter Inverted Data Input, LAN2
3Tx2pTransmitter Non-Inverted Data Input, LAN2
5Tx4nTransmitter Inverted Data Input, LAN4
6Tx4pTransmitter Non-Inverted Data Input, LAN4
8ModSelLModule select pin, the module responds to two-wire serial communication when low level
9ResetLModule Reset
10VccRX+3.3V Power Supply Receiver
11SCL2-wire serial interface clock
12SDA2-wire serial interface data
14Rx3pReceiver Non-Inverted Data Output, LAN3
15Rx3nReceiver Inverted Data Output, LAN3
17Rx1pReceiver Non-Inverted Data Output, LAN1
18Rx1nReceiver Inverted Data Output, LAN1
21Rx2nReceiver Inverted Data Output, LAN2
22Rx2pReceiver Non-Inverted Data Output, LAN2
24Rx4nReceiver Inverted Data Output, LAN4
25Rx4pReceiver Non-Inverted Data Output, LAN4
27ModPrsLThe module is inserted into the indicated pin and grounded in the module
29VccTX+3.3V Power Supply transmitter
30Vcc1+3.3V Power Supply
31LP ModeLow Power Mode
33Tx3pTransmitter Non-Inverted Data Input, LAN3
34Tx3nTransmitter Inverted Data Input, LAN3
36Tx1pTransmitter Non-Inverted Data Input, LAN1
37Tx1nTransmitter Inverted Data Input, LAN1
  1. The module circuit ground is isolated from the module chassis ground within the module.
  2. Open collector; should be pulled up with 4.7k – 10k ohms on host board to a voltage between 3.15Vand 3.6V.

ModSelL Pin

The ModSelL is an input pin. When held low by the host, the module responds to 2-wire serial communication commands. The ModSelL allows the use of multiple QSFP modules on a single 2-wire interface bus. When the ModSelL is “High”, the module will not respond to any 2-wire interface communication from the host. ModSelL has an internal pull-up in the module.

ResetL Pin

Reset. LPMode_Reset has an internal pull-up in the module. A low level on the ResetL pin for longer than the minimum pulse length (t_Reset_init) initiates a complete module reset, returning all user module settings to their default state. Module Reset Assert Time (t_init) starts on the rising edge after the low level on the Reset L pin is released. During the execution of a reset (t_init) the host shall disregard all status bits until the module indicates a completion of the reset interrupt. The module indicates this by posting an IntL signal with the Data_Not_Ready bit negated. Note that on power-up (including hot insertion) the module will post this completion of reset interrupt without requiring a reset.

LPMode Pin

LINKWELL QSFP28 SR4 operate in the low power mode (less than 1.5 W power consumption)

This pin active high will decrease power consumption to less than 1W.

ModPrsL Pin

ModPrsL is pulled up to Vcc on the host board and grounded in the module. The ModPrsL is asserted “Low” when the module is inserted and deasserted “High” when the module is physically absent from the host connector.

IntL Pin

IntL is an output pin. When “Low”, it indicates a possible module operational fault or a status critical to the host system. The host identifies the source of the interrupt by using the 2-wire serial interface. The IntL pin is an open collector output and must be pulled up to Vcc on the host board.

Timing for Soft Control and Status Functions

Initialization Timet_init2000msTime from power on1, hot plug or rising edge of Reset until the module is fully functional2
Reset Init Assert Timet_reset_init2μsA Reset is generated by a low level longer than the minimum reset pulse time present on the ResetL pin.
Serial Bus Hardware Ready Timet_serial2000msTime from power on1 until module responds to data transmission over the 2-wire serial bus
Monitor Data Ready Timet_data2000msTime from power on1 to data not ready, bit 0 of Byte 2, deasserted and IntL asserted
Reset Assert Timet_reset2000msTime from rising edge on the ResetL pin until the module is fully functional2
LPMode Assert Timeton_LPMode100μsTime from assertion of LPMode (Vin:LPMode = Vih) until module power consumption enters lower Power Level
IntL Assert Timeton_IntL200msTime from occurrence of condition triggering IntL until Vout:IntL = Vol
IntL Deassert Timetoff_IntL500μsTime from clear on read3 operation of associated flag until Vout:IntL = Voh. This includes deassert times for Rx LOS, Tx Fault and other flag bits.
Rx LOS Assert Timeton_los100msTime from Rx LOS state to Rx LOS bit set and IntL asserted
Tx Fault Assert Timeton_Txfault200msTime from Tx Fault state to Tx Fault bit set and IntL asserted
Flag Assert Timeton_flag200msTime from occurrence of condition triggering flag to associated flag bit set and IntL asserted
Mask Assert Timeton_mask100msTime from mask bit set4 until associated IntL assertion is inhibited
Mask Deassert Timetoff_mask100msTime from mask bit cleared4 until associated IntlL operation resumes
ModSelL Assert Timeton_ModSelL100μsTime from assertion of ModSelL until module responds to data transmission over the 2-wire serial bus
ModSelL Deassert Timetoff_ModSelL100μsTime from deassertion of ModSelL until the module does not respond to data transmission over the 2-wire serial bus
Power_over-ride or Power-set Assert Timeton_Pdown100msTime from P_Down bit set 4 until module power consumption enters lower Power Level
Power_over-ride or Power-set Deassert Timetoff_Pdown300msTime from P_Down bit cleared4 until the module is fully functional3


  1. Power on is defined as the instant when supply voltages reach and remain at or above the minimum specified value.
  2. Fully functional is defined as IntL asserted due to data not ready bit, bit 0 byte 2 deasserted.
  3. Measured from falling clock edge after stop bit of read transaction.
  4. Measured from falling clock edge after stop bit of write transaction.

Mechanical Dimensions



Ordering information

Part NumberProduct Description
LW-QSFP-40G-ER440GE QSFP+ ER4, up to 40km for G.652 SMF


1. SFF-8436 QSFP+

2. Ethernet 40GBASE-ER4

Important Notice

Performance figures, data and any illustrative material provided in this data sheet are typical and must be specifically confirmed in writing by LINKWELL before they become applicable to any particular order or contract. In accordance with the LINKWELL policy of continuous improvement specifications may change without notice. The publication of information in this data sheet does not imply freedom from patent or other protective rights of LINKWELL or others. Further details are available from any LINKWELL sales representative.