40G QSFP+ ER4 Optical Transceiver - Fiber Optic Cabling Management

396 Fibers FTTH Splitter Cabinet with Insertion Module PLC Splitter - Type B -rear side

396 Fibers FTTH Splitter Cabinet – Type B

2022-01-26

480 Fibers Fiber Distribution Hub (FDH) Cabinet

2022-01-26

LINKWELL 40G QSFP+ ER4 40km optical transceiver is designed for 40G Ethernet and OTN OTU3 links reach up to 40km over Single-Mode Fiber (SMF). It is compliant with the QSFP+ MSA, IEEE 802.3bm 40GBASE-ER4, and OTU3 requirements. The LINKWELL technology enables the integration of 4 transmitters, 4 receivers and an optical MUX/DEMUX into a small form factor package..

Features

4 channels full-duplex transceiver modules
Transmission data rate up to 11Gbps per channel
Compliant with 40GBASE-ER4
4 channels DFB-based CWDM cooling transmitter
4 channels APD ROSA
Low power consumption < 3.5W
Hot-pluggable QSFP+ form-factor
Transmission distance up to 40KM
Duplex LC receptacles
Operating case temperature range 0°C to +70°C
3.3V power supply voltage

Applications

40GBASE-ER4
Infiniband QDR and DDR interconnects

Absolute Maximum Rating

These values represent the damage threshold of the module. Stress in excess of any of the individual Absolute Maximum Ratings can cause immediate catastrophic damage to the module even if all other parameters are within Recommended Operating Conditions.

Parameters	Symbol	Min.	Max.	Unit
Power Supply Voltage	V_CC	-0.3	+3.6	V
Input Voltage	V_in	-0.3	Vcc+0.3
Storage Temperature	T_c	-20	+85	C
Operating Case Temperature	T_c	0	+70	C
Relative Humidity	R_h	5	85	%
Damage Threshold, each Lane	TH	5.5		dBm

Recommended Operating Environment

Recommended Operating Environment specifies parameters for which the electrical and optical characteristics hold unless otherwise noted.

Parameter	Symbol	Min.	Typical	Max	Unit
Power Supply Voltage	V_CC	3.13	3.30	3.47	V
Operating Case Temperature	T_c	0		70	C
Data Rate per Lane	fd	9.95	10.3125	11.15	Gbps
Humidity	R_h	5		85	%
Power Dissipation	Pm		3.5	3.8	W

Optical Characteristics

Parameter	Symbol	Min	Typical	Max	Unit
Lane Wavelength	L0	1264.5	1271	1277.5	nm
	L1	1284.5	1291	1297.5	nm
	L2	1304.5	1311	1317.5	nm
	L3	1324.5	1331	1337.5	nm
Transmitter
SMSR	SMSR	30	–	–	dB
Total Average Launch Power	Pt			10.5	dBm
Average launch power, each lane	Pavg	-2.7	–	4.5	dBm
Optical Modulation Amplitude (OMA), each lane¹	OMA	-1.3		5	dBm
Difference in Launch Power	Ptxd			4.7	dB
Launch Power in OMA		-0.5			dBm
Extinction Ratio	ER	4.5	–	–	dB
TDP, each lane	Tdp			2.6	dB
RIN₂₀OAM	RIN			-128	dB/Hz
Average launch power of OFF				-30	dB
Eye Mask coordinates²: X1, X2, X3, Y1, Y2, Y3	{0.25,0.4,0.45,0.25,0.28.0.4}
Receiver
Damage Threshold, each lane³	THd	-6			dBm
Average Receive Power, each lane		-22.2		-4.5	dBm
Receive Power (OAM), each lane				-4.0	dBm
Receiver Sensitivity (OMA), each Lane (BER = 5×10^-5)	SEN1			-19	dBm
Stressed Receiver Sensitivity (OMA), each lane⁴ (BER = 5×10^-12)	SEN3			-16.8	dBm
Difference in Receive Power between any Two Lanes (OMA)	Prx,diff			3.8	dB
LOS Assert	LOSA	-35			dBm
LOS Deassert	LOSD			-19	dB
LOS Hysteresis	LOSH	0.5			dB

Electrical Characteristics

Parameter	Symbol	Min	Typical	Max	Unit
Transmitter (each lane)
Single-ended Input Voltage Tolerance		-0.3		4.0	V
AC Common-Mode Input Voltage Tolerance		15			mW
Differential Input Voltage		50			mVpp
Differential Input Voltage Swing	Vin			900	mVpp
Differential Input Impedance	Zin	90	100	110	Ohm
Receiver (each lane)
Single-ended Output Voltage		-0.3		4.0	V
AC Common Mode Output Voltage				7.5	mV
Differential Output Voltage Swing		300		850	mVpp
Differential Output Impedance		90	100	110	Ohm

Note

Power-on Initialization Time is the time from when the power supply voltages reach and remain above the minimum recommended operating supply voltages to the time when the module is fully functional

Pin Description

PIN #	Symbol	Description
1	GND	Ground
2	Tx2n	Transmitter Inverted Data Input, LAN2
3	Tx2p	Transmitter Non-Inverted Data Input, LAN2
4	GND	Ground
5	Tx4n	Transmitter Inverted Data Input, LAN4
6	Tx4p	Transmitter Non-Inverted Data Input, LAN4
7	GND	Ground
8	ModSelL	Module select pin, the module responds to two-wire serial communication when low level
9	ResetL	Module Reset
10	VccRX	+3.3V Power Supply Receiver
11	SCL	2-wire serial interface clock
12	SDA	2-wire serial interface data
13	GND	Ground
14	Rx3p	Receiver Non-Inverted Data Output, LAN3
15	Rx3n	Receiver Inverted Data Output, LAN3
16	GND	Ground
17	Rx1p	Receiver Non-Inverted Data Output, LAN1
18	Rx1n	Receiver Inverted Data Output, LAN1
19	GND	Ground
20	GND	Ground
21	Rx2n	Receiver Inverted Data Output, LAN2
22	Rx2p	Receiver Non-Inverted Data Output, LAN2
23	GND	Ground
24	Rx4n	Receiver Inverted Data Output, LAN4
25	Rx4p	Receiver Non-Inverted Data Output, LAN4
26	GND	Ground
27	ModPrsL	The module is inserted into the indicated pin and grounded in the module
28	IntL	Interrupt
29	VccTX	+3.3V Power Supply transmitter
30	Vcc1	+3.3V Power Supply
31	LP Mode	Low Power Mode
32	GND	Ground
33	Tx3p	Transmitter Non-Inverted Data Input, LAN3
34	Tx3n	Transmitter Inverted Data Input, LAN3
35	GND	Ground
36	Tx1p	Transmitter Non-Inverted Data Input, LAN1
37	Tx1n	Transmitter Inverted Data Input, LAN1
38	GND	Ground

The module circuit ground is isolated from the module chassis ground within the module.
Open collector; should be pulled up with 4.7k – 10k ohms on host board to a voltage between 3.15Vand 3.6V.

ModSelL Pin

The ModSelL is an input pin. When held low by the host, the module responds to 2-wire serial communication commands. The ModSelL allows the use of multiple QSFP modules on a single 2-wire interface bus. When the ModSelL is “High”, the module will not respond to any 2-wire interface communication from the host. ModSelL has an internal pull-up in the module.

ResetL Pin

Reset. LPMode_Reset has an internal pull-up in the module. A low level on the ResetL pin for longer than the minimum pulse length (t_Reset_init) initiates a complete module reset, returning all user module settings to their default state. Module Reset Assert Time (t_init) starts on the rising edge after the low level on the Reset L pin is released. During the execution of a reset (t_init) the host shall disregard all status bits until the module indicates a completion of the reset interrupt. The module indicates this by posting an IntL signal with the Data_Not_Ready bit negated. Note that on power-up (including hot insertion) the module will post this completion of reset interrupt without requiring a reset.

LPMode Pin

LINKWELL QSFP28 SR4 operate in the low power mode (less than 1.5 W power consumption)

This pin active high will decrease power consumption to less than 1W.

ModPrsL Pin

ModPrsL is pulled up to Vcc on the host board and grounded in the module. The ModPrsL is asserted “Low” when the module is inserted and deasserted “High” when the module is physically absent from the host connector.

IntL Pin

IntL is an output pin. When “Low”, it indicates a possible module operational fault or a status critical to the host system. The host identifies the source of the interrupt by using the 2-wire serial interface. The IntL pin is an open collector output and must be pulled up to Vcc on the host board.

Timing for Soft Control and Status Functions

Parameter	Symbol	Max	Unit	Conditions
Initialization Time	t_init	2000	ms	Time from power on1, hot plug or rising edge of Reset until the module is fully functional2
Reset Init Assert Time	t_reset_init	2	μs	A Reset is generated by a low level longer than the minimum reset pulse time present on the ResetL pin.
Serial Bus Hardware Ready Time	t_serial	2000	ms	Time from power on1 until module responds to data transmission over the 2-wire serial bus
Monitor Data Ready Time	t_data	2000	ms	Time from power on1 to data not ready, bit 0 of Byte 2, deasserted and IntL asserted
Reset Assert Time	t_reset	2000	ms	Time from rising edge on the ResetL pin until the module is fully functional2
LPMode Assert Time	ton_LPMode	100	μs	Time from assertion of LPMode (Vin:LPMode = Vih) until module power consumption enters lower Power Level
IntL Assert Time	ton_IntL	200	ms	Time from occurrence of condition triggering IntL until Vout:IntL = Vol
IntL Deassert Time	toff_IntL	500	μs	Time from clear on read3 operation of associated flag until Vout:IntL = Voh. This includes deassert times for Rx LOS, Tx Fault and other flag bits.
Rx LOS Assert Time	ton_los	100	ms	Time from Rx LOS state to Rx LOS bit set and IntL asserted
Tx Fault Assert Time	ton_Txfault	200	ms	Time from Tx Fault state to Tx Fault bit set and IntL asserted
Flag Assert Time	ton_flag	200	ms	Time from occurrence of condition triggering flag to associated flag bit set and IntL asserted
Mask Assert Time	ton_mask	100	ms	Time from mask bit set4 until associated IntL assertion is inhibited
Mask Deassert Time	toff_mask	100	ms	Time from mask bit cleared4 until associated IntlL operation resumes
ModSelL Assert Time	ton_ModSelL	100	μs	Time from assertion of ModSelL until module responds to data transmission over the 2-wire serial bus
ModSelL Deassert Time	toff_ModSelL	100	μs	Time from deassertion of ModSelL until the module does not respond to data transmission over the 2-wire serial bus
Power_over-ride or Power-set Assert Time	ton_Pdown	100	ms	Time from P_Down bit set 4 until module power consumption enters lower Power Level
Power_over-ride or Power-set Deassert Time	toff_Pdown	300	ms	Time from P_Down bit cleared4 until the module is fully functional3

Note:

Power on is defined as the instant when supply voltages reach and remain at or above the minimum specified value.
Fully functional is defined as IntL asserted due to data not ready bit, bit 0 byte 2 deasserted.
Measured from falling clock edge after stop bit of read transaction.
Measured from falling clock edge after stop bit of write transaction.

Mechanical Dimensions

Ordering information

Part Number	Product Description
LW-QSFP-40G-ER4	40GE QSFP+ ER4, up to 40km for G.652 SMF

References

1. SFF-8436 QSFP+

2. Ethernet 40GBASE-ER4

Important Notice

Performance figures, data and any illustrative material provided in this data sheet are typical and must be specifically confirmed in writing by LINKWELL before they become applicable to any particular order or contract. In accordance with the LINKWELL policy of continuous improvement specifications may change without notice. The publication of information in this data sheet does not imply freedom from patent or other protective rights of LINKWELL or others. Further details are available from any LINKWELL sales representative.